1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit device. More particularly, the present invention relates to a semiconductor integrated circuit device including a negative power supply circuit for generating a negative internal voltage.
2. Description of the Background Art
FIG. 4 is a schematic block diagram showing the structure of a conventional semiconductor integrated circuit device 50 incorporating a negative internal power supply therein.
Referring to FIG. 4, the conventional semiconductor integrated circuit 50 includes an input terminal PN, a signal line SL, an internal voltage supply line PL for supplying a negative internal voltage Vnn to an internal circuit group, a charge pumping circuit CP for generating a negative voltage on the internal voltage supply line PL, a protection diode DG, and transistor switches T1, T2, T3.
An external electric signal is applied to the input terminal PN. The signal line SL is electrically coupled to the input terminal PN. The charge pumping circuit CP operates when a pump enable signal PE is active. In operation, the charge pumping circuit CP supplies negative charges to the internal voltage supply line PL. The protection diode DG serves to remove a negative surge voltage produced at the input terminal PN.
FIG. 5 is a conceptual diagram illustrating functionality of the protection diode DG.
Referring to FIG. 5, the protection diode DG is connected between the ground voltage Vss and the signal line SL, wherein the forward direction thereof is the direction from the ground voltage Vss toward the signal line SL.
An electric signal to be applied to the input signal PN in the normal operation is set to at least the ground voltage Vss. Therefore, the protection diode DG will not be forward-biased, and the applied electric signal is transmitted to the signal line SL.
When a negative surge voltage is produced at the input terminal PN, the protection diode DG is forward-biased, forming between the signal line SL and the ground voltage Vss a path for removing the negative surge voltage. However, such a protection circuit structure would cause a stationary leak current Ileak to flow into the input terminal PN when a negative voltage VTn needs to be applied to the input terminal PN.
FIG. 6 is a circuit diagram showing the structure of a protection circuit that allows a negative voltage to be applied to the input terminal.
The protection circuit of FIG. 6 additionally includes a transistor switch T1 connected between the anode of the protection diode DG and the ground voltage Vss, and a transistor switch T2 connected between the anode of the protection diode DG and the internal voltage supply line PL.
The transistor switches T2 and T1 are turned ON/OFF in a complementary manner in response to a test mode signal TM and an inverted signal thereof, respectively. The test mode signal TM is activated to H level in the test mode, and inactivated to L level in the normal operation.
In the normal operation, the transistor switches T1 and T2 are turned ON and OFF, respectively, whereby the same protection circuit as that of FIG. 5 is formed for the input terminal PN.
In the test mode, the transistor switches T1 and T2 are turned OFF and ON, respectively, as opposed to the normal operation. As a result, the anode of the protection diode is electrically coupled to the internal voltage supply line PL for supplying a negative voltage. Therefore, even when a negative voltage VTn is applied to the input terminal PN in the test mode, no stationary leak current is produced at the input terminal PN in the range of VTn greater than Vnn+Von (where Von is an ON voltage of the protection diode DG).
Accordingly, the protection circuit of FIG. 6 is conventionally provided in a circuit that requires a negative voltage VTn to be applied to its input terminal. On the other hand, the protection circuit of FIG. 5 having a simplified structure is conventionally provided in a circuit that does not require a negative voltage VTn to be applied to its input terminal.
Referring back to FIG. 4, the transistor switch T3 is turned ON in the test mode so as to electrically couple the input terminal PN and the internal voltage supply line PL to each other through the signal line SL.
In the normal operation, the transistor switch T3 electrically disconnects the input terminal PN and the internal voltage supply line PL from each other. In the normal operation, the charge pumping circuit CP operating in response to activation of the pump enable signal PE supplies negative charges, producing an internal voltage Vnn.
In general, a not-shown control circuit controls the negative voltage produced by the charge pumping circuit by comparing the negative voltage with a prescribed target value and activating or inactivating the pump enable signal according to the comparison result.
In the test mode, various operation tests such as accelerated test must be conducted with various levels of the internal voltage Vnn. Therefore, in the conventional semiconductor integrated circuit device internally generating a negative voltage, the internal voltage Vnn is externally applied in the test mode in order to facilitate adjustment of the voltage level.
The conventional semiconductor integrated circuit device 50 includes the protection circuit of FIG. 6 for the input terminal PN. Therefore, generation of the leak current is prevented even when a negative voltage to be transmitted to the internal voltage supply line PL is applied to the input terminal PN in the test mode.
In response to the need for improved functionality and integration of the semiconductor integrated circuit devices, a plurality of circuits formed on different chips are sealed in the same mold. In such a semiconductor integrated circuit device, the same input terminal may be shared by the plurality of chips.
FIG. 7 is a conceptual diagram illustrating the problems caused by application of negative voltage to the input terminal shared by a plurality of chips.
Referring to FIG. 7, chips CHa and CHb are sealed in the same mold and share the input terminal PN.
The chip CHa is a circuit that does not require a negative internal voltage, and therefore does not require application of external negative voltage during operation including the test mode. Accordingly, a protection diode DGa having the same structure as that of FIG. 5 is provided for a signal line SLa connected to the input terminal PN.
On the other hand, the chip CHb is a circuit that requires a negative internal voltage, and therefore requires application of external negative voltage in the test mode. Accordingly, a protection diode DGb and transistors T1 and T2 are provided so as to form the same protection circuit as that of FIG. 6.
Thus, when a negative voltage is applied to the input terminal PN, the protection diode DGa in the chip CHa is forward-biased, producing a stationary leak current Ileak. This causes latch-up or the like, thereby possibly destabilizing the overall operation of the circuitry.
In other words, the structure of the protection circuit required in the chip CHa varies depending on whether or not the input terminal is shared with another chip CHb that requires application of negative voltage, thereby degrading versatility of the design. Providing the same protection circuit as that of FIG. 6 in every chip would ensure the versatility of the design. However, this requires unnecessary circuit elements, causing increase in size and manufacturing costs of the circuitry.
It is an object of the present invention to provide a semiconductor integrated circuit device capable of adjusting the level of a negative internal voltage produced by an internal power supply circuit, without requiring application of external negative voltage.
A semiconductor integrated circuit device according to the present invention includes: an internal voltage supply line for supplying a negative internal voltage to an internal circuit; a control voltage generation circuit for generating a control voltage according to a difference between a first positive voltage and the internal voltage; and a negative power supply circuit for reducing the voltage on the internal voltage supply line in operation. In a test mode, the negative power supply circuit operates according to a comparison result between a second positive voltage and the control voltage. The second positive voltage corresponds to a target value of the internal voltage.
Preferably, the semiconductor integrated circuit device further includes: first and second input terminals capable of externally receiving first and second electric signals, respectively; and first and second input switching circuits respectively corresponding to the first and second input terminals. The first input switching circuit transmits the first electric signal to the internal circuit in normal operation, and transmits the first electric signal to the control voltage generation circuit in the test mode. The second input switching circuit transmits the second electric signal to the internal circuit in the normal operation, and transmits the second electric signal to the negative power supply circuit in the test mode. In the test mode, the first and second positive voltages are respectively applied through the first and second input terminals.
Preferably, the negative power supply circuit includes a charge pumping circuit for supplying negative charges to the internal voltage supply line when an enable signal is active, and a voltage comparison circuit for amplifying a difference between the second positive voltage and the control voltage to produce the enable signal in the test mode.
Alternatively, the control voltage generation circuit preferably includes a voltage dividing circuit for receiving the first positive voltage and the internal voltage and outputting the control voltage based on the voltage difference multiplied by a prescribed voltage dividing ratio.
More preferably, the voltage dividing circuit includes n resistance units (where n is a natural number) electrically coupled between a first node to which the first positive voltage is transmitted and a second node on which the control voltage is generated, and m resistance units (where m is a natural number) electrically coupled between the internal voltage supply line and the second node. The resistance units are fabricated based on same layout design.
Alternatively, the second positive voltage is more preferably set according to the target voltage, the first positive voltage and the voltage dividing ratio.
Such a semiconductor integrated circuit device operates the negative power supply circuit according to the relation between the second positive voltage and the negative internal voltage, enabling adjustment of the internal voltage level without requiring application of negative voltage.
Moreover, the semiconductor integrated circuit device includes the first and second input switching circuits, enabling external adjustment of the internal voltage level in the test mode by using the same input terminals as those used in the normal operation.
Moreover, the negative power supply circuit can be formed with a charge pumping circuit and an operational amplifier circuit each having a commonly used structure.
Moreover, the voltage dividing circuit is formed from the resistance circuits fabricated based on the same layout design. Therefore, variation in voltage dividing ratio of the voltage dividing circuit due to manufacturing variation in resistance value can be suppressed, enabling accurate adjustment of the internal voltage level while eliminating the effects of the manufacturing process variation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.